1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, particularly to a terminal arrangement thereof.
2. Description of the Related Art
The advancement in a semiconductor technology has brought a progress in high integration and multifunction for LSI (Large Scale Integrated Circuit), further increasing the number of terminals to input/output signals. Complicated function incorporated in the LSI demands a high-level LSI test with the increasing number of terminals used for the test. Since the terminals used for the test are not used by a user, it is desirable to reduce the terminals as much as possible. Although efforts have been made to reduce the number of the terminals used exclusively for the test by sharing with other signal terminals or serializing a test signal, the number is still increasing.
The number of the terminals which can be mounted on a LSI package is physically limited. A technique to increase the number of the test terminals while securing the number of the terminals used by the user is disclosed in Japanese Laid-Open Patent Application JP-P2004-22664A. In a package of a semiconductor device, test terminals are arranged among external wiring terminals which are arranged in a lattice form in a BGA (ball grid array) or a CSP (chip size package). However, since the test terminals are located among the external wiring terminals used for common operations, it is not easy to contact the test terminals to terminals of a test tool.
Japanese Laid-Open Patent Application JP-P2004-342947A also discloses a technique for a semiconductor device including a plurality of connection terminals connected to a mounting substrate and a plurality of test terminals. In the semiconductor device, there are provided a first area wherein the connection terminals are arranged in a lattice form at a predetermined pitch, and a second area wherein the test terminals are arranged in a lattice form at a pitch narrower than the predetermined pitch. The second area is located at the center of a connecting side and surrounded in the outer edge by the first area which is arranged at the peripheral of the connecting side. The second area is also arranged at the peripheral of the connecting side, and the first area is arranged to surround the second area. These connection terminals and test terminals are formed by a solder ball. These connection terminals and test terminals are also formed in a land.
The arrangement of test terminals and common external terminals has been thus developed for improvement. However, when the test terminals are arranged among the external terminals, it is not easy to have a contact between the test terminal and the terminal of the test tool. Moreover, in an arrangement to centralize terminals exclusively used for a test, these terminals are connected to a mounting substrate even though they are not used by the user. Accordingly, the land is provided to connect these terminals exclusively used for the test on the surface of the mounting substrate. This causes the user to have less opening area on the surface of the mounting substrate for wiring as desired.